1. Field of the Invention
This invention relates to electronic circuitry and, more particularly, to a cycle slip framing system and method for use in communication circuits. The cycle slip framing system and method uses a clock generator coupled to a deserializer for selectively adding a bit clock cycle to one or more successive frame clock cycles in order to ensure a character framed by the frame clock and output from the deserializer as a parallel set of related bits matches a character fed to the deserializer as a serial set of related bits clocked by the bit clock.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art or conventional by virtue of their inclusion within this section.
Communication between nodes of a communication system typically involves a serial bitstream. Examples of serial bitstream transfer protocols include Ethernet and Synchronous Optical Network (SONET), as well as numerous others. An integral part of the serialized communication between nodes is the transceiver associated with each node. A transceiver having both a receiver and a transmitter functions not only to recognize the transfer protocols, but also converts the serial bitstream to multiple bitstreams if necessary. The conversion from a relatively high bit rate serial bitstream to a set of relatively low bit rate parallel bitstreams takes place within a receiver and, more specifically, within a deserializer of the receiver.
The serializer and deserializer of the transceiver are normally found within the physical media attachment (PMA) sub-layer of the transceiver. The serializer/deserializer is responsible for supporting multiple communication protocols and allows presentation of encoding schemes to the upper layers of, for example, the Open System Interconnection (OSI) model. A useful feature of a deserializer within the physical layer PMA of the OSI model is that the deserializer can frame its output once synchronization between its serial bitstream of related bits are synchronized to parallel output of related bits.
Framing is used in the normal mode to reframe data in backplane transceivers and, as such, is an integral part of the IEEE 802.3z Gigabit Ethernet and Fibre Channel Standards set forth in http://www.ieee.org and http://www.fibrechannel.org. Framing of serial data is, therefore, the conversion of the serial bitstream to respective frames output in parallel from the deserializer. Certain bits within the serial bitstream are related to one another and thus belong within the same frame output from the deserializer.
Framing can be used for built-in-self-test (BIST) purposes. Many transceiver chips include a pseudo-random bitstream (PRBS) generator in the transmitter channel and a corresponding verification block in the receiver. The function of the verification block is to determine if the received set of related bits (i.e., transmitter-generated character) matches a set of related bits (i.e., receiver-generated character) formed in the verification block of the receiver. Ideally, the transmitter-generated character must match the receiver-generated character at the parallel output of the deserializer. Unfortunately, however, certain related bits can slip from one frame to another depending on the internal operations of the deserializer.
FIG. 1 illustrates a receiver within a communication system transceiver. The receiver 10 includes both a deserializer 12 and clock generator 14. As the serial bitstream 16 is received by deserializer 12, certain related bits (e.g., character A0–A15) are placed in a single frame and output in parallel, as shown by reference numeral 18. The frame of related bits can then be executed upon by core logic 20. A bit clock which transitions according to a bit clock cycle samples the serial bitstream onto the deserializer. Frame 18 transitions from one frame to the next according to a frame clock that transitions within a frame clock cycle.
There are numerous types of deserializers known in the industry. For example, a deserializer can be formed from shift registers. As the serial bitstream is received on the shift registers, the bit clock will shift serial bits into and through the registers, and a character, or frame of related bits, is captured each time the shift registers are filled, once per frame cycle. Another type of deserializer involves a staged or pipelined deserializer. A pipelined deserializer is shown in FIG. 2 as having four stages that will time-division demultiplex an incoming serial bitstream 16 of, for example, 16 bits. Each stage can be clocked by a successively slower clock rate, with the first stage being clocked at ½ the bit rate, and the second stage being clocked at ¼ the bit rate. The clocks sent from a clock generator to deserializer 12 at successive one-half preceding rates are shown as reference numerals 20a–20d. The last stage presents the deserialized frame of related bits 0–15 as shown by reference numeral 22.
The pipelined deserializer architecture is described in U.S. Pat. No. 5,128,940 herein incorporated by reference. Each of the 1-to-2 demultiplexer cells of FIG. 2 is illustrated in FIG. 3 as reference numeral 24. The 1-to-2 demultiplexer cell 24 essentially includes two D-type flip-flops 26 and 28, and a latch 30. Instead of using, for example, two master-slave DFFs for each cell, cost savings can be realized by using latches. The smaller design is set forth in U.S. Pat. No. 6,696,995 herein incorporated by reference.
Regardless of the cell architecture, a 1-to-2 demultiplexer cell samples the incoming serial bitstream at approximately one-half the bitstream rate (f/2 clk), as shown in the timing diagram of FIG. 4. The odd bits (bits a, c, e, etc.) are sampled on the trailing edge of the input clock by DFF 26, and the output of DFF 26 is sampled on the leading edge of the input clock by latch 30 so that the odd bits are aligned with the even bits (bits b, d, f, etc.) that are output from DFF 28.
While pipelined deserializers typically enjoy power saving advantages over conventional shift register deserializers and state machines that sample at the serial bitstream rate, pipelined deserializers typically use multiple latches and flip-flops within each demultiplexer cell. Moreover, as described in U.S. Pat. No. 5,128,940, due to margin differences from one demultiplexer cell to another, related bits A0–A15 may not necessarily appear within the same frame output simultaneously from the final stage of the deserializer. This problem is oftentimes referred to as a “bit shift” or a “bit slip.” A bit shift/slip can be caused by uncertainty in the initial period of the signal input. In order to detect a bit slip, many architectures utilize BIST and PRBS generators to verify if a bit slip has occurred, and to correct the bit slip situation.
One technique for correcting a bit slip occurrence is to apply control signals selectivity to the control clocks forwarded to each stage of the pipelined deserializer. As described in U.S. Pat. No. 5,128,940, logic gates 34 can receive the successively one-half rate clock signals from clock generator 14, along with control signals C0–C3. Depending on the logic state of the control signals, the clocking signals forwarded to each stage of the deserializer can be selectively inverted or non-inverted as shown. By inverting certain select clock signals within select stages, bits of data output from certain stages can be advanced or delayed relative to other bits.
While attempting to address the bit slip problem using logic gates 34 and control signals C0–C3, the bit slip problem may be exasperated. For example, the control signals are typically not synchronous with transitions of the bit clock cycle. Any deviation of the control signal edges will modify the clock signal outputs, even though the clock generator is synchronized to the bit clock. Deviations of the clock signals relative to the serial bitstream will cause the deserializer to encounter incoming jitter, and produce what are known as “invalid bits.” The invalid bits will periodically occur in the interim between those clock differences at the output of the corresponding stages. The invalid bits will ripple through the pipelined architecture and produce unstable and inaccurate results at the output of the deserializer.
In addition, the solution offered in FIG. 5 is indigenous only to a pipelined deserializer. As noted above, there are numerous types of deserializers, such as shift registers or simply state machines that produce frames of parallel output corresponding to a serial bitstream. Having to produce selective clock signals for each successive one-half decreasing clock control signals is, at best, difficult to manage for all 2M types bit shifting possibilities (where M equals the number of deserializer stages), and to maintain for deserializers called upon to deserialize bitstreams in excess of 1.0 GHz.
It would be desirable to introduce a mechanism that alleviates bit slip problems without having to utilize asynchronous control signals and 2M bit shifting possibilities as shown in the solution of FIG. 5. Having M control signals, M control gates, and M asynchronous control signals, it is difficult to alleviate glitches from appearing on the outputs of the gates. Adding additional flip-flops as part of the clock generation scheme in order to avoid metastability and to ensure synchronous operation, only adds additional circuitry to an overall complex solution. It would be desirable to avoid the additional logic gates and/or flip-flops in a staged, pipelined deserializer solution. It would be even further desirable to implement a solution to the bit slip problem for not only pipelined deserializers, but other deserializers as well.